The subject matter of the present application relates to a microelectronic element including a semiconductor chip with structures to achieve improved reliability when assembled with external microelectronic components, including compliant connection structures, and methods of fabricating the microelectronic element.
Semiconductor chips are flat bodies with contacts disposed on a front surface that are connected to internal electrical circuitry of the chip. The chips are typically packaged to form a microelectronic package having terminals that are electrically connected to the chip contacts. The terminals of the package may then be connected to an external microelectronic component, such as a circuit panel.
Microelectronic devices such as semiconductor chips typically require many input and output connections to other electronic components. The input and output contacts of a semiconductor chip or other comparable device are generally disposed in grid-like patterns that substantially cover a surface of the device (commonly referred to as an “area array”) or in elongated rows which may extend parallel to and adjacent each edge of the device's front surface, or in the center of the front surface. Typically, devices such as chips must be physically mounted on a substrate such as a printed circuit board, and the contacts of the device must be electrically connected to electrically conductive features of the circuit board.
Semiconductor chips are commonly provided in packages that facilitate handling of the chip during manufacture and during mounting of the chip on an external substrate such as a circuit board or other circuit panel. For example, many semiconductor chips are provided in packages suitable for surface mounting. Numerous packages of this general type have been proposed for various applications. Most commonly, such packages include a dielectric element, commonly referred to as a “chip carrier” with terminals formed as plated or etched metallic structures on the dielectric. These terminals typically are connected to the contacts of the chip itself by features such as thin traces extending along the chip carrier itself and by fine leads or wires extending between the contacts of the chip and the terminals or traces. In a surface mounting operation, the package is placed onto a circuit board so that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads. The package can be permanently bonded in place by heating the assembly so as to melt or “reflow” the solder or otherwise activate the bonding material.
Many packages include solder masses in the form of solder balls, typically about 0.1 mm and about 0.8 mm (5 and 30 mils) in diameter, attached to the terminals of the package. A package having an array of solder balls projecting from its bottom surface is commonly referred to as a ball grid array or “BGA” package. Other packages, referred to as land grid array or “LGA” packages are secured to the substrate by thin layers or lands formed from solder. Packages of this type can be quite compact. Certain packages, commonly referred to as “chip scale packages,” occupy an area of the circuit board equal to, or only slightly larger than, the area of the device incorporated in the package. This is advantageous in that it reduces the overall size of the assembly and permits the use of short interconnections between various devices on the substrate, which in turn limits signal propagation time between devices and thus facilitates operation of the assembly at high speeds.
Mismatches or differences between coefficients of thermal expansion (“CTE”) of the components in such a package can adversely impact their reliability and performance. In an example, a semiconductor chip may have a lower CTE than that of a substrate or printed circuit board to which it is mounted. As the chip undergoes heating and cooling due to the use cycle thereof, the components will expand and contract according to their differing CTEs. In this example, the substrate will expand more and at a greater rate than the semiconductor die. This can cause stress in the solder masses (or other structures) used to both mount and electrically connect the semiconductor die and the substrate. Such stress can cause the solder mass to disconnect from either or both of the semiconductor die or the substrate, thereby interrupting the signal transmission that it otherwise facilitates. Various structures have been used to compensate for such variations in CTE, yet many fail to offer a significant amount of compensation on a scale appropriate for the fine pitch arrays being increasingly utilized in microelectronic packages.